Memory and method for fabricating it

ABSTRACT

Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

CLAIM FOR PRIORITY

This application claims the benefit of priority to German ApplicationNo. 10 2005 024 855.1, filed in the German language on May 31, 2005, thecontents of which are hereby incorporated by reference.

TECHNICAL FIELD OF THE INVENTION

The invention relates to a memory and method for fabricating a memorywhich is formed as an integrated circuit in a semiconductor substrate.

BACKGROUND OF THE INVENTION

Semiconductor memories, principally DRAMs, are generally realized as amemory cell matrix on a semiconductor wafer. In this case, the memorycells comprise a storage capacitor and a selection transistor. During areading or writing operation, the storage capacitor is charged ordischarged with an electrical charge corresponding to the respectivedata unit, via the selection transistor. For this purpose, the selectiontransistor is addressed via a bit or word line with the aid of aperipheral logic having switching transistors.

A significant main focus in the technological development ofsemiconductor memories, in particular DRAMs, is the storage capacitor.In order to provide for a sufficient storage capacitance in conjunctionwith a small cross-sectional area, the storage capacitors are thereforerealized three-dimensionally in the form of trench capacitors. In thecase of such trench capacitors, a trench is etched into thesemiconductor substrate, the trench being filled with a dielectricintermediate layer and a first storage electrode, a doped region of thesemiconductor substrate around the trench serving as a second storageelectrode. The selection transistor of the memory cell is usually formedas a planar field effect transistor alongside the trench capacitor onthe semiconductor surface, one source/drain electrode being connected tothe inner electrode of the trench capacitor.

On account of the still increasing miniaturization of the memory cells,even in the case of trench capacitors additional possibilities are beingsought for simultaneously reducing the area requirement and increasingthe capacitor capacitance. One possibility for increasing thecapacitance in the case of trench capacitors is to use very thininsulator layers having a high dielectric constant as a dielectricintermediate layer between the capacitor electrodes. Materialcombinations comprising thin silicon dioxide and silicon nitride layersare conventionally used as storage dielectric in the case of trenchcapacitors, the inner electrode of the trench capacitor generallycomprising doped polysilicon.

With trench capacitors constructed in this way, it becomes more and moredifficult, however, in the context of the cell area that constantlydecreases from technology generation to technology generation, toprovide for a sufficient storage capacitance. For sub-100 nm structures,therefore, consideration is being given to a material modification inthe case of the storage dielectric. The aim is for the materials thatare conventionally used for the dielectric intermediate layer in trenchcapacitors to be replaced by materials which are distinguished by ahigher dielectric constant and thus enable the area-specific storagecapacitance to be increased. Such materials, what are known as high-kdielectrics, are e.g. hafnium oxide, zirconium oxide or oxides of thelanthanide series.

However, these high-k dielectrics are generally thermally stable only ina temperature range below 800° C. and are therefore suitable only to avery limited extent for replacing the conventional dielectricintermediate layers in trench capacitors, since temperatures above 1000°C. are often required when forming memory cells in the context ofsilicon planar technology, particularly when activating dopings of theswitching transistors. Although high-k dielectrics having a higherthermal stability are also known, these high-temperature high-kdielectrics can only be integrated with very great difficulty into thestandard process for fabricating trench capacitors in the context ofsilicon planar technology and, in particular, can be formed as extremelythin layers only with very great difficulty.

SUMMARY OF THE INVENTION

The invention relates to a method for fabricating a memory which isformed as an integrated circuit in a semiconductor substrate andcomprises storage capacitors and switching transistors, and to a memoryfabricated in accordance with this method, in particular a dynamicrandom access memory (DRAM).

In accordance with a first embodiment of the invention, there is amethod for fabricating a memory which is formed as an integrated circuitin a semiconductor substrate and comprises storage capacitors andswitching transistors comprises the following: the storage capacitorsare formed in the semiconductor substrate in each case in a trench andhave an outer electrode layer, which is formed around the trench, adielectric intermediate layer, which is embodied on the trench wall andcomprises a high-k dielectric that is unstable at high temperatures ofabove 800° C., and an inner electrode layer, with which the trench isessentially filled; the switching transistors are formed in thesemiconductor substrate in each case in a surface region and have afirst source/drain doping region, a second source/drain doping regionand an intervening channel, which is separated from a gate electrode byan insulator layer; the dielectric intermediate layer of the storagecapacitors is embodied in a manner spaced apart from the surface of thesemiconductor substrate at least by a magnitude corresponding to thedepth to which the source/drain doping regions of the switchingtransistors extend in the semiconductor substrate; and a short-timeheat-treatment method is used for the thermal activation of the dopantsin the source/drain doping zones of the switching transistors attemperatures of above 1000° C., during which method the thermal energyis coupled in from the wafer surface for a few microseconds tomilliseconds.

In accordance with a second embodiment of the invention, there is amethod for fabricating a memory which is formed as an integrated circuitin a semiconductor substrate and comprises storage capacitors andswitching transistors comprises the following: a dielectric intermediatelayer of the trench capacitors is formed with a low-temperature high-kdielectric, the dielectric intermediate layer of the storage capacitorsbeing embodied in a manner spaced apart from the surface of thesemiconductor substrate at least by a magnitude corresponding to thedepth to which the source/drain doping regions of the field effecttransistors extend; and one of the methods laser annealing, flashannealing and SPER annealing is used for the thermal activation of thedopants in the source/drain doping zones of the switching transistors inthe semiconductor substrate.

In accordance with a third embodiment of the invention, the memory whichis formed as an integrated circuit in a semiconductor substratecomprises storage capacitors and switching transistors. The storagecapacitors in the semiconductor substrate are formed in each case in atrench and have an outer electrode layer, which is formed around thetrench, a dielectric intermediate layer, which is embodied on the trenchwall, and an inner electrode layer, with which the trench is essentiallyfilled. The switching transistors in the semiconductor substrate areformed in each case in a surface region and have a first source/draindoping region, a second source/drain doping region and an interveningchannel, which is separated from a gate electrode by an insulator layer.The dielectric intermediate layer of the storage capacitors comprises alow-temperature high-k dielectric, the source/drain doping regions ofthe switching transistors extending to a depth of approximately 200 nmfrom the surface of the semiconductor substrate, and the dielectricintermediate layer of the storage capacitors being spaced apart from thesurface of the semiconductor substrate by at least 200 nm.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and features of the present invention willbecome clear from the following description taken in conjunction withthe accompanying drawings in which:

FIG. 1 shows a circuit diagram of a dynamic memory cell in a DRAMmemory.

FIGS. 2 to 7 show an embodiment of a method according to the inventionfor fabricating a DRAM memory according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

According to the invention, in the case of a memory which is formed asan integrated circuit in a semiconductor substrate and comprises storagecapacitors and switching transistors, the storage capacitor being formedin the semiconductor substrate as a trench capacitor and the switchingtransistors being formed as field effect transistors, the dielectricintermediate layer of the trench capacitors is formed with a high-kdielectric that is unstable at a high temperature, in particular atemperature above 800° C., the dielectric intermediate layer of thestorage capacitors being embodied in a manner spaced apart from thesurface of the semiconductor substrate at least by a magnitudecorresponding to the depth to which the source/drain doping regions ofthe field effect transistors extend.

The buried embodiment of the dielectric intermediate layer of the trenchcapacitors affords the possibility of fabricating the dielectricintermediate layer on a low-temperature high-k dielectric which isdistinguished by a high dielectric constant and hence an increasedstorage capacitance for trench capacitors. Although the low-temperaturehigh-k dielectric is only stable in a temperature range below 800° C.,that is to say a temperature range far below the temperature of above1000° C. required for the activation of the dopants in the source/draindoping regions of the switching transistors, the buried design of thedielectric intermediate layer in such a way that the intermediate layeris arranged deeper than the doping regions of the switching transistorsmakes it possible to ensure that the high temperatures for activatingthe dopants in the doping zones do not damage the low-temperature high-kdielectric layer situated deeper.

In this case, it is preferred for the dielectric intermediate layer ofthe trench capacitors to be formed in a manner spaced apart from thesurface of the semiconductor substrate by at least 200 nm.

Furthermore, it is preferred in this case to implement the dopants ofthe source/drain regions of the switching transistors in thesemiconductor substrate with the aid of laser annealing, flash annealingor SPER annealing. With these heating processes, it is possible to heatonly the surface region of the semiconductor substrate in which thedopants are arranged to the temperature of at least 1000° C. requiredfor the activation of the dopants.

The invention is explained on the basis of a process sequence forforming a DRAM memory. In this case, the individual structures of theDRAM memory are preferably formed with the aid of silicon planartechnology, which comprises a sequence of individual processes that ineach case act over the whole area of the surface of a siliconsemiconductor wafer, a local alteration of the silicon substrate beingcarried out in a targeted manner by means of suitable masking layers.During the DRAM memory fabrication, a multiplicity of dynamic memorycells are formed simultaneously in this case.

FIG. 1 shows a circuit diagram of a one-transistor memory cell such asis predominantly used in DRAM memories. The one-transistor memory cellcomprises a storage capacitor 1 and a selection transistor 2. In thiscase, the selection transistor 2 is formed as a field effect transistorand has a first source/drain electrode 21 and a second source/drainelectrode 23, between which an active region 22 is arranged. Arrangedabove the active region are a gate insulator layer 24 and gate electrode25, which act like a plate capacitor which can influence the chargedensity in the active region 22 in order to form or block acurrent-conducting channel between the first source/drain electrode 21and the second source/drain electrode 23.

The second source/drain electrode 23 of the selection transistor 2 isconnected to a first electrode 11 of the storage capacitor 1 via aconnecting line 4. A second electrode 12 of the storage capacitor 1 isin turn connected to a capacitor plate 5, which is preferably common toall the storage capacitors of the DRAM memory cell arrangement. Thefirst electrode 21 of the selection transistor 2 is furthermoreconnected to a bit line 6 in order that the information stored in thestorage capacitor 1 in the form of charges can be read in and out. Inthis case, the reading-in or reading-out operation is controlled via aword line 7, which is at the same time the gate electrode 25 of theselection transistor 2, in order, by applying a voltage, to produce acurrent-conducting channel in the active region 22 between the firstsource/drain electrode 21 and the second source/drain electrode 23.

In many cases trench capacitors are used as storage capacitors indynamic memory cells since a significant reduction of the memory cellarea can be achieved by means of the three-dimensional structure. Withincreasing miniaturization of the memory cells, given a scaling size ofless than 100 nm, additional measures are necessary, however, in orderto be able to fulfill the three basic requirements made of a dynamicmemory cell in a DRAM memory, namely a sufficiently large storagecapacitance of approximately 25 to 40 fF, which is necessary forreliable detection of the charge stored in the storage capacitor, apacking-dense and structure-friendly cell layout, which provides for aminimum chip area and thus for reduced costs, and also a highperformance of the selection transistor, in particular a high read-inand read-out current with an at the same time low reverse current.

In order to provide for a sufficient storage capacitance in the case ofa reduced trench capacitor cross section, according to the invention thedielectric intermediate layer made of silicon dioxide and/or siliconnitride layers that is conventionally used between the two capacitorelectrodes in the trench capacitors is replaced by a high-k dielectrichaving a higher dielectric constant. This procedure makes it possible toreduce the trench capacitor dimensioning and at the same time tomaintain the storage capacitance required for reliable detection.

Preferred materials in this case are binary oxides, such as e.g.tantalum oxide (Ta₂O₅) having a dielectric constant of 25 and atemperature stability up to 800° C. The use of aluminum oxide (Al₂O₃)having a dielectric constant of 10 and a temperature stability up to830° C. is also advantageous. Moreover, hafnium oxide (HfO₂) having adielectric constant of 50 to 60, and zirconium oxide (ZrO₂) having adielectric constant of 11 to 25 are also suitable for use as a high-kdielectric. Lanthanum oxide (L₂O₃) having a dielectric constant of 20 to25, and yttrium oxide (Y₂O₃) having a dielectric constant of 11 to 12may also be used. These materials are stable in the temperature range upto 800° C.

Furthermore, aluminum oxide compounds are taken into consideration ashigh-k dielectrics. In particular compounds with hafnium, zirconium andlanthanum, for example Hf—Al—O, Zr—Al—O or La—Al—O, are suitable forthis. Furthermore, high-k dielectrics may also be produced from silicatecompounds, such as e.g. Hf—Si-0, Zr—Si—O, La—Si—O or Y—Si—O. Thealuminum and silicate compounds are distinguished by a dielectricconstant of above 14 with a temperature stability up to 900°.

Moreover, further individual or mixed oxides or nitrides of the fourthor fifth secondary group and of the third and fourth main groups aresuitable as high-k dielectrics, but the high-k dielectrics, particularlywhen they are suitable for use in the context of silicon planartechnology for application as a dielectric intermediate layer in thetrench capacitor, have a temperature stability of generally not morethan 800° C.

However, in the standard process sequences for fabricating memories inthe context of silicon planar technology, temperatures of above 1000° C.generally occur after the introduction of the dielectric intermediatelayer. This applies in particular to the required heating for activatingthe dopants in the source/drain doping zones of the field effecttransistors which are used both as selection transistors in the memorycells but also as drive transistors in the peripheral logic region ofthe DRAM memory.

In order to prevent these high temperatures of above 1000° C. fromdamaging the low-temperature high-k dielectric layer of the trenchcapacitors, according to the invention the low-temperature high-kdielectric layer is embodied in a manner spaced apart from the surfaceof the semiconductor substrate at least by a magnitude corresponding tothe depth to which the first source/drain doping region and the secondsource/doping drain region of the field effect transistors extend in thesemiconductor substrate. In the case of shallow source/drain dopingzones such as are generally embodied in planar field effect transistorsused as switching transistors in DRAM memories, the doping zones extendto a depth of approximately 200 nm, so that the dielectric intermediatelayer of the trench capacitors is embodied in a manner spaced apart fromthe surface of the semiconductor substrate at least by this magnitude.

At the same time, the semiconductor substrate heating processes whichare performed in the context of the fabrication of the DRAM memory afterthe introduction of the low-temperature high-k dielectric as dielectricintermediate layer in the trench capacitors are carried out in such away that only the surface region of the semiconductor substrate abovethe buried low-temperature high-k dielectric layers is heated. Thisapplies in particular to the thermal activation of the dopants in thesource/drain doping zones of the switching transistors.

According to the invention, short-time heat treatment methods in whichthe thermal energy is coupled in for a few microseconds to millisecondsfrom the wafer surface are used in this case as surface heating methods.It is preferred in this case to carry out short-time heating by means oflaser beams (laser annealing), by means of a flash high-energy lamp(flash assisted rapid thermal processing) or by means of SPER technology(solid phase epitaxial regrowth), in which a recrystallization of thelayer is achieved. These heating methods ensure that the hightemperatures of above 1000° C. for activating the dopants in thesource/drain doping zones occur only in the doping zone itself, that isto say at the semiconductor surface above the low-temperature high-kdielectric layers.

FIGS. 2 to 7 show a process sequence according to the invention forfabricating a DRAM memory in silicon planar technology, a cross sectionthrough a silicon wafer being shown schematically in each case. A memorycell region and a peripheral logic region are provided here on thesilicon wafer. The memory cells of the DRAM memory are composed of aplanar field effect transistor and a trench capacitor. The peripherallogic region contains various components, the switching transistorsbeing fabricated in CMOS technology.

The starting material is a p⁻-doped silicon substrate 100, in which ann⁻-doped memory cell region 101 is defined by means of a lithographystep and a subsequent ion implantation. A multilayer masking layer 102for trench etching is then applied on the semiconductor substrate andthe storage capacitor region is defined with the aid of a furtherlithography step. An etching mask is then produced from the maskinglayer 102 with the aid of an anisotropic etch. An anistropic siliconetch is subsequently carried out in order to form trenches 103 for thestorage capacitors which have a depth of 3 to 10 μm. FIG. 2 shows across section through the silicon wafer after embodiment of the trenches103.

In a next process sequence, the buried outer capacitor electrode is thenformed by producing an n⁺-doped buried plate electrode 104. Afterembodiment of the buried plate electrode 104, a dielectric intermediatelayer 105 is then produced in the trenches 103, the low-temperaturehigh-k dielectric specified above being used as material combination forthe dielectric intermediate layer. A cross section through the siliconwafer after the deposition of the low-temperature high-k dielectric ofthe storage capacitors is shown in FIG. 3.

In a further process sequence, the inner capacitor electrode is thenformed. In this case, n⁺-doped polysilicon or else a metallic fillingmaterial may be used as material for the inner capacitor electrode.Noble metal but also conductive metal oxide and nitride compounds suchas TiN or RuO may be used in this case. The metallic layer has a lowerresistance compared with the n⁺-doped polysilicon.

After the filling of the trenches 103, the electrode layer 106 is etchedback by 200 to 2000 nm below the surface of the silicon substrate 100and the low-temperature high-k dielectric layer is removed on theuncovered walls of the trenches 103. A silicon dioxide layer 107 is thenproduced as a collar on the uncovered trench walls and the trench isfilled with n⁺-doped polysilicon 108. A cross section through thesilicon wafer after the filling of the trenches with n⁺-dopedpolysilicon 108 is illustrated in FIG. 4.

A further process sequence then involves producing buried strap contacts109 for the connection of the selection transistors that are formedlater and are arranged in planar fashion alongside the trench.Afterward, insulation regions 110 are then defined with the aid of alithographic step and after these regions have been etched free they arefilled with silicon dioxide, preferably with the aid of the TEOS methodin a temperature range of below 800° C.

The selection transistors of the memory cells and also the switchingtransistors—fabricated in CMOS technology—of the peripheral logic regionare then fabricated in a further process sequence. For this purpose, ina first step with the aid of a lithography process and an ionimplantation, the n-channel transistor regions are defined by producinga p⁻-doped well 111 and the p-channel transistor regions are defined byproducing an n⁻-doped well 112. The multilayer gate electrode tracks 113of the transistors are then produced with the aid of a furtherlithography process. FIG. 5 shows a cross section through the siliconwafer after the formation of the gate electrode tracks 113.

After the production of the gate electrode tracks 113, LDD zones 114 forthe n-channel transistors may be defined with the aid of a lithographystep and be doped by a subsequent ion implantation e.g. of arsenic.Analogously, the LDD zones 115 for the p-channel transistors are thendefined with the aid of a lithography step and doped by ion implantatione.g. of boron. FIG. 6 shows a cross section through the silicon waferafter the formation of the LDD zones of the n- and p-channeltransistors.

In a further process step, spacers 116 are then produced around the gateelectrode tracks 113. Afterward, the highly doped regions of thesource/drain electrode 117, 118 of the n-channel transistors andp-channel transistors are then formed with the aid of two successive ionimplantations. In this case, arsenic, for example, is used as n⁺-typedoping and boron, for example, is used as p⁺-type doping. In this case,the doping depth is chosen such that it lies above the dielectricintermediate layer 105 of the trench capacitors which comprises alow-temperature high-k dielectric.

The activation of the dopants is then performed with the aid of a laserannealing, a flash annealing or an SPER annealing. These short-time heattreatment methods for activating the dopants make it possible to delimitheating of the silicon wafer to the surface region in which the dopingis introduced. This ensures that the temperatures of above 1000° C. thatare required in this activation process do not damage the high-kdielectric layer 105 of the trench capacitors, which is thermallyunstable above 800° C.

In the case of flash annealing, the procedure is generally such that thesilicon wafer is heated to a first temperature of between 200° C. and600° C., preferably between 400° C. and 500° C., by means of a firstlamp. The desired temperature of above 1000° C. is then generated by ahigh-energy flash lamp, the flash lamp being active for between 1 and100 msec, preferably 30 msec, and having a flash energy of 15 to 35mJ/cm², preferably 25 to 29 mJ/cm².

In the case of laser annealing the short-time heat treatment isperformed by means of local temperature coupling-in with the aid of alaser beam that scans the wafer surface.

In the case of the SPER method a recrystallization of the doping regionis performed, heating being effected to a temperature of 600° C. to 800°C. for up to 1 min with a temperature rise of K/10 to K/150 sec,preferably greater than K/50 sec. It is preferred in this case for atemperature of 700° C. to be held for 5 sec.

The procedure according to the invention, in which only thesemiconductor surface in the region of the doping implantation is heatedto a great extent, makes it possible to achieve a sufficient dopantactivation of the source/drain regions of the switching transistorswithout damaging the low-temperature high-k dielectric layers of thetrench capacitors.

With a further process sequence, the source/drain regions of theswitching transistors are then contact-connected and connected up to oneanother via interconnects. FIG. 7 shows a cross section through thesilicon wafer after the contact-connection 119 and formation of thefirst metalization plane 120.

1. A method for fabricating a memory which is formed as an integratedcircuit in a semiconductor substrate and comprises storage capacitorsand switching transistors; comprising: forming the storage capacitors inthe semiconductor substrate in each case in a trench and having an outerelectrode layer, which is formed around the trench, a dielectricintermediate layer, which is embodied on the trench wall and comprises ahigh-k dielectric that is unstable at high temperatures of above 800°C., and an inner electrode layer, with which the trench is essentiallyfilled; forming the switching transistors in the semiconductor substratein each case in a surface region and having a first source/drain dopingregion, a second source/drain doping region and an intervening channel,which is separated from a gate electrode by an insulator layer;embodying the dielectric intermediate layer of the storage capacitors ina manner spaced apart from the surface of the semiconductor substrate atleast by a magnitude corresponding to the depth to which thesource/drain doping regions of the switching transistors extend in thesemiconductor substrate; and using a short-time heat-treatment methodbeing used for the thermal activation of the dopants in the source/draindoping zones of the switching transistors at temperatures of above 1000°C., during which method the thermal energy is coupled in from the wafersurface for a few microseconds to milliseconds.
 2. The method as claimedin claim 1, wherein the dielectric intermediate layer of the storagecapacitors being spaced apart from the surface of the semiconductorsubstrate by at least 200 nm.
 3. The method as claimed in claim 1,wherein the activation of the dopants of the source/drain doping regionsof the switching transistors in the semiconductor substrate beingperformed with the aid of one of the methods laser annealing, flashannealing and SPER annealing.
 4. The method as claimed in claim 3,wherein in the case of flash annealing the semiconductor wafer beingheated to a first temperature of between 200° C. and 600° C. by means ofa first lamp and then a temperature of above 1000° C. being generated bya high-energy flash lamp, the flash lamp being active for between 1 and100 msec and having a flash energy of 15 to 35 mJ/cm².
 5. The method asclaimed in claim 3, wherein in the case of flash annealing thesemiconductor wafer being heated to a first temperature of between 400°C. and 500° C. by means of a first lamp and then a temperature of above1000° C. being generated by a high-energy flash lamp, the flash lampbeing active for 30 msec and having a flash energy of 25 to 29 mJ/cm².6. The method as claimed in claim 3, wherein in the case of laserannealing the short-time heat treatment being performed by means oflocal temperature coupling-in with the aid of a laser beam that scansthe wafer surface.
 7. The method as claimed in claim 3, wherein in thecase of the SPER method a recrystallization of the source/drain dopingregions of the switching transistors being performed, heating beingeffected to a temperature of 600° C. to 800° C. for up to 1 min with atemperature rise of K/10 to K/150 sec.
 8. The method as claimed in claim3, wherein in the case of the SPER method a recrystallization of thesource/drain doping regions of the switching transistors beingperformed, heating being effected with a temperature rise of greaterthan K/50 sec and a temperature of 700° C. being held for 5 sec.
 9. Amethod for fabricating a memory which is formed as an integrated circuitin a semiconductor substrate and comprises storage capacitors andswitching transistors, comprising: forming the storage capacitor in thesemiconductor substrate as a trench capacitor and the switchingtransistors being formed as field effect transistors; forming adielectric intermediate layer of the trench capacitors with alow-temperature high-k dielectric, the dielectric intermediate layer ofthe storage capacitors being embodied in a manner spaced apart from thesurface of the semiconductor substrate at least by a magnitudecorresponding to the depth to which the source/drain doping regions ofthe field effect transistors extend; and using one of the methods laserannealing, flash annealing and SPER annealing for the thermal activationof the dopants in the source/drain doping zones of the switchingtransistors in the semiconductor substrate.
 10. The method as claimed inclaim 9, wherein in the case of flash annealing the semiconductor waferbeing heated to a first temperature of between 200° C. and 600° C. bymeans of a first lamp and then a temperature of above 1000° C. beinggenerated by a high-energy flash lamp, the flash lamp being active forbetween 1 and 100 msec and having a flash energy of 15 to 35 mJ/cm². 11.The method as claimed in claim 9, wherein in the case of flash annealingthe semiconductor wafer being heated to a first temperature of between400° C. and 500° C. by means of a first lamp and then a temperature ofabove 1000° C. being generated by a high-energy flash lamp, the flashlamp being active for 30 msec and having a flash energy of 25 to 29mJ/cm².
 12. The method as claimed in claim 9, wherein in the case oflaser annealing the short-time heat treatment being performed by meansof local temperature coupling-in with the aid of a laser beam that scansthe wafer surface.
 13. The method as claimed in claim 9, wherein in thecase of the SPER method a recrystallization of the source/drain dopingregions of the switching transistors being performed, heating beingeffected to a temperature of 600° C. to 800° C. for up to 1 min with atemperature rise of K/10 to K/150 sec.
 14. The method as claimed inclaim 9, wherein in the case of the SPER method a recrystallization ofthe source/drain doping regions of the switching transistors beingperformed, heating being effected with a temperature rise of greaterthan K/50 sec and a temperature of 700° C. being held for 5 sec.
 15. Amemory which is formed as an integrated circuit in a semiconductorsubstrate, comprising: storage capacitors formed in the semiconductorsubstrate in each case in a trench and having an outer electrode layer,which is formed around the trench, a dielectric intermediate layer,which is embodied on the trench wall, and an inner electrode layer, withwhich the trench is essentially filled; and switching transistors formedin the semiconductor substrate in each case in a surface region andhaving a first source/drain doping region, a second source/drain dopingregion and an intervening channel, which is separated from a gateelectrode by an insulator layer, wherein the dielectric intermediatelayer of the storage capacitors comprising a low-temperature high-kdielectric, the source/drain doping regions of the switching transistorsextending to a depth of approximately 200 nm from the surface of thesemiconductor substrate, and the dielectric intermediate layer of thestorage capacitors being spaced apart from the surface of thesemiconductor substrate by at least 200 nm.
 16. The memory as claimed inclaim 15, the low-temperature high-k dielectric comprising at least oneof the following materials: tantalum oxide, aluminum oxide, hafniumoxide, zirconium oxide, lanthanum oxide, yttrium oxide, an aluminumoxide compound with hafnium, zirconium or lanthanum, a silicate compoundwith hafnium, zirconium, lanthanum or yttrium.